All-digital phase-locked-loop (ADPLL) circuits have been proposed for use in radiofrequency (RF) and other circuits. Fast frequency acquisition is crucial for phase-locked loops operation. A time-to-digital converter (TDC) is configured to provide tuning of the ADPLL. Current ADPLL circuits utilize sensors configured to detect variations in process, voltage, and temperature (collectively referred to as “PVT”) during operation of the ADPLL to calibrate the TDC. Such PVT-based calibration must be designed for each specific use case and increases the cost and complexity of ADPLL circuit design in CMOS-based circuits.
Current methods using PVT-based calibration require long delay cell stages and cannot fix TDC resolution/in-band noise in frequency synthesizer applications. Further, current PVT-based calibration cannot compensate for PVT variations (such as process variations), but instead must be individually tuned for each circuit.